The present invention is directed to integrated circuits. More particularly, the invention provides systems and methods for reducing electromagnetic interference (EMI) using switching frequency jittering in the quasi-resonant mode. Merely by way of example, the invention has been applied to a power conversion system. But it would be recognized that the invention has a much broader range of applicability.
Switching-mode power conversion systems often have switching frequencies in the range of tens of kHz and hundreds of kHz. Parasitic capacitance and parasitic inductance usually exist in the switching-mode power conversion systems. Electromagnetic interference (EMI) generated by a switching-mode power conversion system often needs to be reduced in order to avoid interfering significantly with other power components. To reduce the size of a switching-mode power conversion system, the switching frequency of the switching-mode power conversion system usually needs to be increased. But increasing the switching frequency often exacerbates the problems related to EMI and switching loss.
A fixed-frequency controller with frequency jittering is often used in a power conversion system to reduce the EMI. FIG. 1 is a simplified diagram showing a conventional power conversion system including a fixed-frequency pulse-width-modulation (PWM) controller. The power conversion system 100 includes a fixed-frequency PWM controller 102, a primary winding 118, a secondary winding 120, a power switch 122, a current sensing resistor 124, a feedback-and-isolation component 126, a rectifying diode 128 and a capacitor 130. The fixed-frequency PWM controller 102 includes an oscillator 104, a PWM comparator 106, a flip-flop 108, a gate driver 110, a diode 112, and two resistors 114 and 116. The fixed-frequency PWM controller 102 further includes three terminals 132, 134 and 136. For example, the power switch 122 is a field-effect transistor (FET), a bipolar junction transistor (BJT), or an insulated-gate bipolar transistor (IGBT).
The switching frequency of the power conversion system 100 is often determined by the oscillator 104. To reduce the EMI, the oscillator 104 is often used to perform switching frequency jittering in different ways, e.g., ramping up and down the switching frequency of the power conversion system 100, or using a pseudo-random generator to change the switching frequency.
FIG. 2 is a simplified conventional timing diagram for the power conversion system 100 showing frequency jittering by ramping up and down the switching frequency by the oscillator 104. The waveform 202 represents the switching frequency of the power conversion system 100 as a function of time. The waveform 204 represents turned-on and turned-off conditions of the switch 122 as a function of time. For example, if the waveform 204 is at a logic high level, the switch 122 is closed (e.g., on), and if the waveform 204 is at a logic low level, the switch 122 is open (e.g., off). Two time periods T1 and T2 are shown in FIG. 2. The time period T1 starts at time t0 and ends at time t1, and the time period T2 starts at time t1 and ends at time t2. For example, t0≤t1≤t2.
During the time period T1, the switching frequency of the power conversion system 100 ramps up from a minimum frequency 206 (at t0) to a maximum frequency 208 (at t1) as shown by the waveform 202. The frequency of the switch 122 being turned on and off increases as shown by the waveform 204. During the time period T2, the switching frequency of the power conversion system 100 ramps down from the maximum frequency 208 (at t1) to the minimum frequency 206 (at t2) as shown by the waveform 202. The frequency of the switch 122 being turned on and off decreases as shown by the waveform 204.
The magnitude of the frequency jittering is usually controlled within a certain range to avoid audio noise caused by excessive frequency jittering. For example, if the fixed-frequency system 100 has a switching frequency of about 60 kHz, the range of frequency jittering can be ±4%. That is, the switching frequency range of the system 100 is 60 kHz±2.4 kHz. The frequency range for energy distribution of an nth-order harmonic is ±2.4 nkHz. The total harmonics energy of the fixed frequency system 100 remains the same, while the harmonic energy amplitude at each harmonic frequency reduces. Thus, the conduction EMI of the system 100 is often improved.
In operation, the system 100 usually has a parasitic inductance Lk in the transformer including the primary winding 118 and the secondary winding 120. The power switch 122 often has a parasitic capacitance Cp between the terminals 138 and 140. The parasitic inductance Lk and the parasitic capacitance Cp often not only reduce the system efficiency, but increase the EMI. For example, when the power switch 122 is open (e.g., off), the parasitic inductance Lk and the parasitic capacitance Cp often cause resonation, and a high peak voltage is generated at the terminal 138. Then after the primary inductance Lp of the transformer is demagnetized, the primary inductance Lp and the parasitic capacitance Cp often cause resonation, and the voltage of the terminal 138 oscillates with decreasing amplitude. But the amplitude of the voltage of the terminal 138 is often at a high level. When the power switch 122 is closed (e.g., on) during a next period, the parasitic capacitance Cp often discharges through the power switch 122, and generates a high peak current including many harmonics, which usually exacerbates the problems related to switching loss and EMI.
Quasi-resonant (QR) techniques can be implemented to take advantage of the parasitic inductance and the parasitic capacitance existing in a power conversion system to improve system efficiency. FIG. 3 is a simplified diagram showing a conventional fly-back power conversion system including a QR controller. The power conversion system 300 includes a QR controller 302, a primary winding 304, a secondary winding 306, a power switch 308, a rectifying diode 310, a capacitor 312, an output load 316, and an auxiliary winding 330. For example, the power switch 308 is a field-effect transistor (FET), a bipolar junction transistor (BJT) or an insulated-gate bipolar transistor (IGBT).
As shown in FIG. 3, the fly-back conversion system 300 has a parasitic inductance 318 (e.g., Lk) in the transformer including the primary winding 304 and the secondary winding 306, and a primary inductance 334 (e.g., Lp) of the transformer. The power switch 308 has a parasitic capacitance 314 (e.g., Cp) between the terminals 320 and 322.
In operation, if the power switch 308 is closed (e.g., on), a current 324 (e.g., Ip) flows through the power switch 308. For example, the voltage between the terminals 320 and 324 of the power switch 308 is determined based on the following equation:Vds=Vin+N×Vout  (Equation 1)wherein Vds represents the voltage between the terminals 320 and 324 of the power switch 308, Vin represents an input voltage 326 on the primary side of the system 300, and Vout represents an output voltage 328 on the secondary side of the system 300. Additionally, N represents a turns ratio between the primary winding 304 and the secondary winding 306.
FIG. 4 is a simplified conventional timing diagram for the power conversion system 300. The waveform 402 represents the voltage between the terminals 320 and 322 of the power switch 308 (e.g., Vds) as a function of time. The waveform 404 represents turned-on and turned-off conditions of the switch 308 as a function of time. The waveform 406 represents the current 324 that flows through the power switch 308 as a function of time. For example, if the waveform 404 is at a logic high level, the switch 308 is closed (e.g., on), and if the waveform 404 is at a logic low level, the switch 308 is open (e.g., off).
Five time periods Ton, Tr, Tdemag, Toff, and Ts are shown in FIG. 4. The time period Ton starts at time t0 and ends at time t1, and the time period Tdemag starts at time t1 and ends at time t2. The time period Tr starts at the time t2 and ends at time t3, and the time period Toff starts at the time t1 and ends at the time t3. The time period Ts starts at t0 and ends at t3. For example, t0≤t1≤t2≤t3. The time periods Tdemag and Tr are within the time period Toff. The time period Ts is the switching period of the system 300, and includes the time period Ton and the time period Toff.
During the time period Ton, the power switch 308 is closed (e.g., on) as shown by the waveform 404. The voltage between the terminals 320 and 322 (e.g., Vds) keeps at a low value 412 (e.g., approximately zero as shown by the waveform 402). The current that flows through the power switch 308 increases over time from a low value 410 (e.g., approximately zero at t0) to a peak value 408 (e.g., Ipk at t1) as shown by the waveform 406.
At the beginning of the time period Tdemag (e.g., at t1), the power switch 308 becomes open (e.g., being turned off) as shown by the waveform 404. The voltage between the terminals 320 and 322 (e.g., Vds) increases from the low value 412 (e.g., approximately zero at t1) as shown by the waveform 402. The current that flows through the power switch 308 drops from the peak value 408 to a low value 414 (e.g., approximately zero) as shown by the waveform 406.
During the time period Tdemag, the power switch 308 remains open (e.g., off) as shown by the waveform 404. The current that flows through the power switch 308 remains at the low value 414 (e.g., approximately zero) as shown by the waveform 406. For example, the voltage between the terminals 320 and 322 (e.g., Vds) can be determined according to Equation 1. The parasitic capacitance 314 (e.g., Cp) and the parasitic inductance 318 (e.g., Lk) cause high frequency resonation. The primary inductance of the transformer 334 (e.g., Lp) is demagnetized.
At the end of the time period Tdemag (e.g., at t2), the demagnetization of the primary inductance 334 (e.g., Lp) is completed. The QR controller 302 detects a falling edge of a voltage 332 (e.g., VDEM) at the auxiliary winding 330 that indicates the completion of the demagnetization.
During the time period Tr, the power switch 308 remains open (e.g., off) as shown by the waveform 404. The current that flows through the power switch 308 remains at the low value 414 (e.g., approximately zero) as shown by the waveform 406. The primary inductance 334 (e.g., Lp) and the parasitic capacitance 314 (e.g., Cp) cause resonation. The voltage between the terminals 320 and 322 (e.g., Vds) decreases from a high value 418 (e.g., at t2) to a valley value 416 (e.g., at t3) as shown by the waveform 402. When the switch 308 is closed (e.g., on) at the beginning of a next switching period, the voltage between the terminals 320 and 322 (e.g., Vds) is at the valley value 416. The current peaks caused by the parasitic capacitance 314 (e.g., Cp) through the power switch 308 is often reduced, and thus the switching loss and the EMI of the system 300 is often improved.
As shown in FIG. 4, the time period Tr during which the parasitic capacitance 314 (e.g., Cp) and the primary inductance 334 (e.g., Lp) resonate is less than the switching period Ts of the system 300. The system 300 operates approximately in a boundary-conduction mode (BCM). The output power of the system 300 can be determined based on the following equation.
                              P          out                =                  η          ×                                    I              pk                        2                    ×                      [                                          N                ×                                  (                                                            V                      out                                        +                                          V                      F                                                        )                                ×                                  V                                      in                    ⁢                    _                    ⁢                    DC                                                                                                N                  ×                                      (                                                                  V                        out                                            +                                              V                        F                                                              )                                                  +                                  V                                      in                    ⁢                    _                    ⁢                    DC                                                                        ]                                              (                  Equation          ⁢                                          ⁢          2                )            where Pout represents the output power of the system 300, η represents the power transfer efficiency of the system 300, and Ipk represents the peak current on the primary side of the system 300. Additionally, N represents a turns ratio between the primary winding 304 and the secondary winding 306, Vout represents the output voltage on the secondary side of the system 300, and VF represents the voltage drop on the rectifying diode 310. Furthermore, Vin_DC represents the voltage level of the input voltage 326 (e.g., a power-factor-correction output voltage, or a line input rectified voltage), and D represents a turn-on duty cycle of the power switch 308.
The switching frequency of the system 300 can be determined based on the following equation.
                              f          s                =                                                            η                ×                                  V                                      in                    ⁢                    _                    ⁢                    DC                                                                                                                      ⁢                    2                                                                              2                ×                                  L                  P                                ×                                  P                  out                                                      ×                          D              2                                =                                    η                              2                ×                                  L                  P                                ×                                  P                  out                                                      ×                                          [                                                      N                    ×                                          (                                                                        V                          out                                                +                                                  V                          F                                                                    )                                                                            1                    +                                                                  N                        ×                                                  (                                                                                    V                              out                                                        +                                                          V                              F                                                                                )                                                                                            V                                                  in                          ⁢                          _                          ⁢                          DC                                                                                                                    ]                            2                                                          (                  Equation          ⁢                                          ⁢          3                )            where fs represents the switching frequency of the system 300, Lp represents the inductance of the primary winding 304, and Pout represents the output power of the system 300. Additionally, η represents the power transfer efficiency of the system 300, Ipk represents the peak current on the primary side of the system 300, and N represents a turns ratio between the primary winding 304 and the secondary winding 306. Furthermore, Vout represents the output voltage on the secondary side of the system 300, VF represents the voltage drop on the rectifying diode 310, Yin_DC represents the voltage level of the input voltage 326 (e.g., a power-factor-correction output voltage, or a line input rectified voltage), and D represents the turn-on duty cycle of the power switch 308.
According to Equations 1 and 2, the switching frequency of the system 300 often remains approximately constant, if the output load 316 and the input voltage 326 do not change. The frequency range for energy distribution of the conduction EMI is usually narrow. The conduction EMI cannot be reduced significantly in the conventional fly-back power conversion system 300 using the QR techniques.
FIG. 5 is a simplified diagram showing a conventional power conversion system including a QR controller. The power conversion system 500 includes a QR controller 502, a primary winding 504, a secondary winding 506, a power switch 508, a rectifying diode 510, a capacitor 512, an error-amplification-and-isolation component 516, a current sensing resistor 518, an auxiliary winding 520, and two resistors 522 and 524. The QR controller 502 includes a demagnetization detection component 526, a flip-flop 528, a gate driver 530, a PWM comparator 532, a diode 534, and two resistors 536 and 538. The QR controller 502 further includes four terminals 540, 542, 544 and 546. For example, the power switch 508 is a field-effect transistor (FET), a bipolar junction transistor (BJT) or an insulated-gate bipolar transistor (IGBT).
As shown in FIG. 5, the error-amplification-and-isolation component 516 receives the output voltage 548 on the secondary side of the system 500, and outputs a feedback signal 550 to the terminal 540 (e.g., terminal FB). The feedback signal 550 is received by at least the diode 534. In response, the resistors 536 and 538 generate a signal 552 to a non-inverting input terminal of the PWM comparator 532.
A primary current 554 that flows through the primary winding 504 is sensed by the current sensing resistor 518, which in response outputs the sensed signal 556 to the terminal 546 (e.g., terminal CS). The sensed signal 556 is received at an inverting input terminal of the PWM comparator 532. The PWM comparator 532 generates a comparison signal 558 based on the signal 552 and the sensed signal 556.
The resistors 522 and 524 receive an auxiliary current 560 that flows through the auxiliary winding 520, and in response outputs a demagnetization signal 562 to the terminal 542 (e.g., terminal dem). The demagnetization detection component 526 receives the demagnetization signal 562, and outputs a detection signal 564. The flip-flop 528 receives the comparison signal 558 at one input terminal, and the detection signal 564 at another input terminal. In response, the flip-flop 528 outputs a signal 566 to the gate driver 530. The gate driver 530 outputs a gate drive signal 568 through the terminal 544 (e.g., terminal gate) to drive the power switch 508.
The feedback signal 550 generated by the error-amplification-and-isolation component 516 is often used to control the peak values of the current 554 in order to regulate the output voltage 548. To make the system 500 operate stably, the error-amplification-and-isolation component 516 is usually compensated, and the bandwidth is often limited to below one-tenth or one-fifteenth of the switching frequency. Similar to what is discussed in FIGS. 3 and 4, the conduction EMI cannot be reduced significantly in the conventional power conversion system 500 using the conventional QR controller 502.
Hence it is highly desirable to improve techniques for reducing the EMI.